Design and Analysis of a Comparator for Flash ADC
Senthil Sivakumar M1, Sowmya Priya M2
1Senthil Sivakumar M, Assistant Professor, Department of ECE, Vignans Foundation of Science, Technology and Research, Guntur (Andhra Pradesh), India.
2Sowmya Priya M, PG Student, Department of ECE, Vignans Foundation of Science, Technology and Research, Guntur (Andhra Pradesh), India.
Manuscript received on 14 February 2019 | Revised Manuscript received on 05 March 2019 | Manuscript Published on 08 June 2019 | PP: 368-372 | Volume-7 Issue-5S4, February 2019 | Retrieval Number: E10770275S419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Flash ADC is the fastest ADC in the analog to digital conversion which is employed popularly in high-frequency applications. The comparator is a major block used in the flash ADC for analog to digital conversion. The use of comparators count is varied depends on the resolution of the flash ADC. Comparator count increases as 2n for an n-bit resolution flash ADC. As the resolution of the ADC increases, the use of comparator count in the ADC is also increased as large which increases the area utilization of the ADC. This paper analyzes the area and power utilization factor of the various types of comparators in order to solve the area utilization problem in the flash ADC. The comparator circuits are simulated in cadence virtuoso using CMOS 180nm technology. The power, area and delay of the different comparators are compared for best utilization in the flash ADC.
Keywords: ADC, Comparator, Resolution, CMOS, Track and Latch, TIQ.
Scope of the Article: Predictive Analysis