Finfet Based Two Stage Dynamic Comparators for Low Power High Speed Adcs
Sarada Musala1, Gonuguntla Sailakshmi2
1Sarada Musala, Department of ECE, Vignan’s Foundation for Science, Technology and Research, Vadlamudi (Andhra Pradesh), India.
2Gonuguntla Sailakshmi, Department of ECE, Vignan’s Foundation for Science, Technology and Research, Vadlamudi (Andhra Pradesh), India.
Manuscript received on 14 February 2019 | Revised Manuscript received on 05 March 2019 | Manuscript Published on 08 June 2019 | PP: 313-316 | Volume-7 Issue-5S4, February 2019 | Retrieval Number: E10660275S419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes two stage dynamic comparators. These are designed for high speed low power ADC’s. Comparator is a device which compares the two input signals and provides differential outputs. It is used in the devices which measure and digitize the analog signals i.e., ADCs, Zero crossing detectors, relaxation oscillators and level shifters. These are used in front end designs of biomedical, digital imaging, communication and digital signal processing applications. In the proposed designs, dynamic latch circuit is used to reduce the area and delay because dynamic logic circuits require less area with high speed than the static designs. Depending on the clock signal, the dynamic latch is evaluated in pre-charge and evaluation phases. The proposed designs have been simulated in Cadence using 180 nm CMOS and 18 nm FINFET technologies. These designs offer low power with high speed and better PDP.
Keywords: Dynamic Comparator, ADC, Dynamic Latch, CMOS Technology, FINFET Technology, PDP.
Scope of the Article: Low-power design