Simulation and Optimization of a Partial Gate All Around Cylindrical Tunnel FET
Kanjalochan Jena1, Brinda Bhowmick2, Srimanta Baishya3
1K.Jena, Research scholar, Department of ECE, NIT Silchar (Assam), India.
2B.Bhowmick, Asst. Prof., Department of ECE, NIT Silchar (Assam), India.
3S. Baishya, Prof., Department of ECE, NIT Silchar (Assam), India.
Manuscript received on 21 November 2013 | Revised Manuscript received on 28 November 2013 | Manuscript published on 30 November 2013 | PP: 43-45 | Volume-2 Issue-5, November 2013 | Retrieval Number: E0856112513/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper represents a partial gate all around cylindrical tunnel FET. In this device gate is applied over half of the channel and the entire source and hetero-gate dielectric is used. A compact electrostatic model for potential of the proposed device is formulated using central difference technique considering 16×16 matrix. Optimization has been done for various gate materials since electrical parameters like OFF current, ON current, threshold voltage, vertical electric field are strong function of gate work function. Furthermore, the proposed device is also compared with cuboidal partially gate-all-around 3D structure for gate oxide scaling. The results of the potential model show good agreement with the simulated data obtained from TCAD simulation.
Keywords: Band-to-Band Tunneling, Partial Gate all Around, Work Function.
Scope of the Article: Network Function Virtualization