FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder
L.Malathi1, A.Bharathi2, A.N.Jayanthi3
1L.Malathi, Assistant Professor, Department of Electronics and Communication Engineering Sri Ramakrishna Institute of Technology, Coimbatore, India.
2Dr.A.Bharathi, Professor & Head, Department of Information Technology Bannari Amman Institute of Technology, Erode, India.
3Dr.A.N.Jayanthi, Associate Professor, Department of Electronics and Communication Engineering Sri Ramakrishna Institute of Technology, Coimbatore, India.
Manuscript received on November 12, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on 30 November, 2019. | PP: 8445-8449 | Volume-8 Issue-4, November 2019. | Retrieval Number: D9714118419/2019©BEIESP | DOI: 10.35940/ijrte.D9714.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Though Multipliers play a major role in all digital processing systems, still there is a research challenge related with area, delay, power, speed and accuracy parameters. Basically multipliers contains more number of adders (i.e.,) multiplication is done by repetitive additions. Highest care should be taken on adders. Partial Products (PP) part is middle process between multiplier, multiplicand and final addition. Next one about the methodology that Serial/parallel, Pipeline/parallel, Floating/decimal, Array, Binary/BCD, Fixed/Variable, Gate Level/Transistor Level. All the predecessors are having more controversy parameters. The forthcoming research concentrated on parallel, pipelining, decimal, binary and transistor level.
Keywords: Kogge Stone Adder, Flagged Perfix Adder, Area, Delay, Power.
Scope of the Article: FPGAs.