Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units
Parthibaraj Anguraj1, Thiruvenkadam Krishnan2, Kumaresan Natesan3
1Parthibaraj Anguraj*, Junior Research Fellow, Department Of Electronics And Communication Engineering, Sri Eshwar College Of Engineering, Coimbatore, Tamilnadu, India.
2Thiruvenkadam Krishnan, Assistant Professor, Department Of Electronics And Communication Engineering, K. Ramakrishnan College Of Technology, Trichy, Tamilnadu, India.
3Kumaresan Natesan, Assistant Professor, Department Of Electronics And Communication Engineering, Anna University Regional Campus, Coimbatore, Tamilnadu, India. .
Manuscript received on November 12, 2019. | Revised Manuscript received on November 24 2019. | Manuscript published on 30 November, 2019. | PP: 10189-10198 | Volume-8 Issue-4, November 2019. | Retrieval Number: D8604118419/2019©BEIESP | DOI: 10.35940/ijrte.D8604.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.
Keywords: Fast Fourier Transform, Butterfly Unit, complex multiplier, FPGA.
Scope of the Article: FPGA.