A Low Input Referred Noise Dynamic Comparator for High Speed Applications 
D Pavan kumar Sharma1, P.Sreehari Rao2
1D Pavan kumar sharma *, Department of Electronics and communication, National Institute of Technology, Warangal, Telangana, India.
2P.Sreehari Rao, Department of Electronics and communication, National Institute of Technology, Warangal, Telangana, India.
Manuscript received on November 12, 2019. | Revised Manuscript received on November 25, 2019. | Manuscript published on 30 November, 2019. | PP: 4768-4772 | Volume-8 Issue-4, November 2019. | Retrieval Number: D6881118419/2019©BEIESP | DOI: 10.35940/ijrteD6881.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz.
Keywords: Dynamic Comparator, Offset Voltage, Kickback Noise.
Scope of the Article: Foundations Dynamics.