Low Glitch & Low Power Dual Edge Triggered D-Type Flip Flops for Integrated Applications
Viresh Pandey1, Pramod Kumar Jain2, Devendra Singh Ajnar3
1Viresh Pandey, Department of Electronics & Instrumentation, Shri G.S. Institute of Technology & Science, Indore (M.P), India.
2Pramod Kumar Jain, Department of Electronics & Instrumentation, Shri G.S. Institute of Technology & Science, Indore (M.P), India.
3Devendra Singh Ajnar, Department of Electronics & Instrumentation, Shri G.S. Institute of Technology & Science, Indore (M.P), India.
Manuscript received on 15 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 July 2019 | PP: 5906-5912 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3766078219/2019©BEIESP | DOI: 10.35940/ijrte.B3766.078219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents Dual Edge Triggered (DET) master slave D-Type flip flops for glitch free, low power, low delay, low silicon area and low Power Delay Product (PDP). This DET master slave D-Type flip flops are compared against the existing DET flip flops using 45nm & 180nm CMOS technology which has been simulated using Cadence Virtuoso. The proposed DET master slave D-Type flip flops has reduced the number of transistors in use for operation, which leads to low glitch, low power and low delay design. Paper consist glitch free DET master slave D-Type flip flops analysis for power, delay and PDP. The proposed DET flip flop is also simulated and implemented for 18nm Fin-FET in Cadence Tool.
Index Terms: Dual Edge Triggered (DET), Master Slave, D-Type Flip Flop, Glitch, Clock Signal, Power, Delay, Power Delay Product (PDP).
Scope of the Article: Nanometer-Scale Integrated Circuits