Deeper Insight of Various Full-Adder Designs with Various Techniques and Technology
Preeti Singh1, Shobha Sharma2, Ashish Singh3
1Preeti Singh, Electronics and Communication, Indira Gandhi Delhi Technical University for Women, Delhi, India.
2Dr Shobha Sharma, (Corresponding Author) Faculty, Electronics and Communication, Indira Gandhi Delhi Technical University for Women, Delhi
3Ashish Singh Electronics and Communication, RJIT, BSF Academy, India.
Manuscript received on 15 March 2019 | Revised Manuscript received on 21 March 2019 | Manuscript published on 30 July 2019 | PP: 5041-5046 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1561078219/19©BEIESP | DOI: 10.35940/ijrte.B1561.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper various type of full adder circuits with high-speed operation have been analyzed. Power Consumption, Speed and Area are important factors of the design aspect of full adder circuit. Many researchers have worked on full adder designs using various technologies. Present paper deals with literature analysis based on full adder designs.
Index Term: Power Consumption, Speed, Delay, Full –Adder, Power Delay Products.
Scope of the Article: Optical and High-Speed Access Networks