TCAD Simulation of Nano-Crystal Floating Gate EEPROM
Surya Deo Chaudhary1, Ashish Pathak2
1Dr. Surya Deo Chaudhary, Department of Electronics & Communication Engineering, Noida Institute of Engineering and Technology, (Uttar Pradesh), India.
2Ashish Pathak, Department of Physics, Noida Institute of Engineering and Technology, (Uttar Pradesh), India.
Manuscript received on 14 October 2019 | Revised Manuscript received on 23 October 2019 | Manuscript Published on 02 November 2019 | PP: 2156-2157 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B12260982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1226.0982S1119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The present invention relates to a Nano crystal floating gate memory which is reflected as a future nonvolatile memory. The reason behind this reflection is its invulnerability in tunnel oxide to weak-point leakage and therefore its higher scalability of tunnel oxide thickness and utilization of power. The Foremost feature attribute in NCM is that it functions on a low value of voltage.
Keywords: TCAD, MOSFET, Tunnel Oxide Layer, EEPROM.
Scope of the Article: Digital Clone or Simulation