FIR Filter Design Using Floating Point Column Bypassing Technique
Jency Rubia J1, Sathish Kumar G.A2
1Jency Rubia J, Research Scholar, Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai (Tamil Nadu), India.
2Sathish Kumar G.A, Professor, Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai (Tamil Nadu), India.
Manuscript received on 04 July 2019 | Revised Manuscript received on 14 August 2019 | Manuscript Published on 27 August 2019 | PP: 409-413 | Volume-8 Issue-2S4 July 2019 | Retrieval Number: B10790782S419/2019©BEIESP | DOI: 10.35940/ijrte.B1079.0782S419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.
Keywords: Column Bypassing Technique, Error Reduction Algorithms, FIR Filter, Fixed-Width Multiplier, Nearest Rounding, Wrap Overflow.
Scope of the Article: Low-power design