Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications
S V V Satyanarayana1, K Teja Sri2, K Madhavi3, G Jhansi4, B Jaya Sri5
1Dr. S V V Satyanarayana, Department of Electronics and Communication Engineering, Sri Vasavi Engineering College, Pedatadepalli (A.P), India.
2K Teja Sri, Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.
3K Madhavi, Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.
4G Jhansi, Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.
5B Jaya Sri, Department of Electronic and Communication, Sri Vasavi Engineering College, Tadepalligudem, Pedatadepalli (A.P), India.
Manuscript received on 26 March 2023 | Revised Manuscript received on 06 April 2023 | Manuscript Accepted on 15 May 2023 | Manuscript published on 30 May 2023 | PP: 27-32 | Volume-12 Issue-1, May 2023 | Retrieval Number: 100.1/ijrte.A75640512123 | DOI: 10.35940/ijrte.A7564.0512123
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.
Keywords: FIR filters, CIC filters, VLSI architecture, Verilog.
Scope of the Article: Low-power design