Floor Planning of 256 Tap FIR filter using Flip-Chip Technology for IR Drop and EM Effect Avoidance
Srinath Balasubramaniam1, Nivethaa N2
1Srinath Balasubramanian, Assistant Professor at the Dept. of ECE. SRM Institute of Science and Technology, Chennai, India.
2Nivethaa N, Pusuing M. Techin VLSI Design from SRM Institute of Science and Technology, Chennai, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 08 May 2019 | Manuscript published on 30 May 2019 | PP: 363-371 | Volume-8 Issue-1, May 2019 | Retrieval Number: A3367058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Flip chip ICs are one of the emerging packaging technology that offers high integration density with an increase in the number of IO pads. Voltage drop in the power/Ground network of these designs has becomes a serious concern in the design of modern chips. This paper presents a co-synthesis process to determine the optimal mesh network in order to achieve the power constraints. Given a fixed locality of P/G pin, the proposed method performs incremental floorplanning to effectively reduce the IR drop and EM violations. First, a 256 tap FIR filter is implemented in flipchip package operating with multiple supply voltages and then it performs the proposed methodology to accomplish the power constraints. Simulation results on 256 tap FIR filter circuit shows that the presented algorithm successfully eliminates the IR drop and EM violations at the floorplanning stage while preserving the floorplan quality and P/G network.
Index: Floorplanning, P/G Network, IR Aware Incremental Floorplan, IR drop, Multiple Supply Voltage.
Scope of the Article: Problem Solving and Planning