Energy Efficient D Flip Flop Using AVLG Technique with Static Body Biasing
Anwesha Deb1, Shobha Sharma2, Amita Dev3
1Anwesha Deb, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
2Shobha Sharma, (Corresponding Author) Assistant Professor, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
3Amita Dev, Pro Vice Chancellor, Indira Gandhi Delhi Technical University for Women, Delhi, India.
Manuscript received on 09 April 2019 | Revised Manuscript received on 14 May 2019 | Manuscript published on 30 May 2019 | PP: 1699-1702 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1360058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The world is growing at an ultra-fast speed and so is the technology. Today small devices with maximum efficiency and minimum power are in demand and so came the flip flops. They are used in large number of applications ranging from data storage to microprocessors. In this paper, a new circuit for D flip flop is proposed which uses two techniques, namely, AVL and body biasing techniques on 5 transistor TSPC D flip flop. The D flip flop circuit based on 5 transistor TSPC AVL technique is already existing. The body biasing technique is applied on the already existing circuit in order to minimize the power consumption. The simulations of these circuits are done on Cadence Virtuoso tool using 180nm technology. The detailed description is given in this research paper.
Index Terms: AVL Techniques, D Flip Flop, Static Body Biasing, TSPC Logic.
Scope of the Article: Energy Efficient Building Technology