Energy Efficient D Flip-Flop using MTCMOS Technique with Static Body Biasing
Shivali1, Shobha Sharma2, Amita Dev3
1Shivali, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
2Shobha Sharma, (Corresponding Author) Assistant Professor, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
3Amita Dev, Pro Vice Chancellor, Indira Gandhi Delhi Technical University for Women, Delhi, India.
Manuscript received on 09 April 2019 | Revised Manuscript received on 15 May 2019 | Manuscript published on 30 May 2019 | PP: 1696-1698 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1359058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The need of fast and energy efficient devices is growing day-by-day and so flip flops are coming into picture. For many digital devices, flip flops are the elementary unit for construction. They are termed as one bit memory element. This paper enumerates, anew circuit design of D flip flop which consists of two techniques, i.e., MTCMOS technique and body biasing technique. The 5 transistor TSPC D flip flop using MTCMOS technique already exists. The body biasing technique is used on the already present circuit with the aim of achieving a new energy efficient design for D flip flop. The simulations are done using the Cadence Virtuoso 180nm technique.
Index Terms: Body Biasing, D Flip-Flop, MTCMOS Technique, TSPC Logic.
Scope of the Article: Energy Efficient Building Technology