Low Power Hardware Efficient Comparator using Full Swing 3T XNOR
Riya Sara Joy1, Reneesh C Zacharia2
1Riya Sara Joy, P.G. Scholar, Department of Electronics and Communication, Mangalam College of Engineering, Ettumanoor Kottayam (Kerala), India.
2Reneesh C Zacharia, Assistant Professor, Department of Electronics and Communication, Mangalam College of Engineering, Ettumanoor Kottayam (Kerala), India.
Manuscript received on 07 June 2019 | Revised Manuscript received on 30 June 2019 | Manuscript Published on 04 July 2019 | PP: 1000-1003 | Volume-8 Issue-1S4 June 2019 | Retrieval Number: A11840681S419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper describes a new full swing 3T XNOR for low power, hardware efficient comparator design. This 3 transistor(3T) XNOR can achieve full output swing at an operating voltage one with lesser power and dimension of energy(power delay product) compared to the conventional XNOR designs. Thereby proposed low power area efficient comparator circuits can play a vital role in encryption systems, error detecting circuits, complex ALUs, and DSPs, where power, speed, and area are the major constraints. By realizing this hardware efficient proposed comparator, achieve complex circuit optimization. The proposed hardware is deliberate using CADENCE 5.1.0 EDA tool and simulated in spectre virtuoso.
Keywords: Comparator; Full Swing 3T XNOR; Low Power; Optimization; Cadence(Tool).
Scope of the Article: Low-power design