Design and Implementation of High Performance CMOS Latch Designs in VDSM Technology
S. Govindarajulu1, B. Doss2, T. Naresh3
1Dr. S. Govindarajulu, Professor, Department of ECE, G.P.R.E.C Autonomous, Kurnool (Andhra Pradesh), India.
2Dr. B. Doss, Associate Professor, Department of ECE, G.P.R.E.C Autonomous, Kurnool (Andhra Pradesh), India.
3T. Naresh, Assistant Professor, Department of ECE, G.P.R.E.C Autonomous, Kurnool (Andhra Pradesh), India.
Manuscript received on 06 June 2019 | Revised Manuscript received on 30 June 2019 | Manuscript Published on 04 July 2019 | PP: 849-852 | Volume-8 Issue-1S4 June 2019 | Retrieval Number: A11560681S419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this work, 3 high performance, low value and strong latches area unit projected in sixty five nm CMOS VDSM (very deep sub micron) Headway. The predicted catches place unit absolutely merciless toward brief insufficiencies at their interior focus focuses and yield focuses free of the period of the CMOS semiconductor. The anticipated locks bear brief blames at any rate the force of the putting iota. The predicted catches supply high pace, higher reliableness to brief deformities with diminishing expenses concerning force and area.
Keywords: CMOS, PDP, VDSM (Very Deep Sub Micron), Performance, Latch of the Static Nature, Reliability of the Circuit.
Scope of the Article: Low-power design