Data Integrity Maintenance using and Logic Feed based Low Power SRAM Cell
A. Dinesh Babu1, J. Akash2, Vishnu Varadhan Janardhanan3
1A. Dinesh Babu, Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Vadapalani Campus, Chennai (Tamil Nadu), India.
2J. Akash, Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Vadapalani Campus, Chennai (Tamil Nadu), India.
3Vishnu Varadhan Janardhanan, Post Graduation, Department of Electrical Engineering, University of Texas at Dallas, Houston, TX USA.
Manuscript received on 04 June 2019 | Revised Manuscript received on 29 June 2019 | Manuscript Published on 04 July 2019 | PP: 467-473 | Volume-8 Issue-1S4 June 2019 | Retrieval Number: A10870681S419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Continuous Nano-Scaling of transistors, coupled with increasing demand for ultra-low power applications where expanded system operation time under limited energy resource constraints increments the susceptibility of VLSI circuits designs to soft errors. The robustness and energy efficiency are vital design parameters for Body Sensor Nodes, intelligent wearable,Internet of Things and space mission projects. In contrast for graphics (GPU) processors, servers, high-end applications and general purpose processors, energy is consumed for higher performance. To meet the increasing demand for larger embedded memories like SRAM in highly integrated SoCs to support a wide dimensions of functions. As a result, further strengtheningthe design constraints on performance, energy, and power is needed. In general SRAMs dominates as being a basic foundational building block for such memory arrays. Any minor modifications in the fundamental unit will have significant impact in the overall design. This work presents a AND gate feed based SRAM cell, which significantly upgrades read and write static noise margin (SNM) and utilizes low power. Simulation was done using 180nm technology library file of Cadence virtuoso design software. The finalresults shows how the cell achieves the lowest leakage power dissipation among the other cells in the existing state of art designs. Investigations are also done in terms of process voltage, average power variations etc.
Keywords: Static Random Access Memory, Static Noise Margin, Silicon on Chip, Internet of Things.
Scope of the Article: Low-power design