Implementation of Low Power and Memory Efficient 2D FIR Filter Architecture
Venkata Krishna Odugu1, C Venkata Narasimhulu2, K Satya Prasad3
1Venkata Krishna Odugu, Department of Electronics & Communication Engineering, Research Scholar JNTUK, Kakinada, India.
2C. Venkata Narasimhulu, Department of Electronics & Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, India.
3K. Satya Prasad, Rector, Vignan/s Foundation for Science, Technology & Research, Guntur, India.
Manuscript received on 04 April 2019 | Revised Manuscript received on 09 May 2019 | Manuscript published on 30 May 2019 | PP: 927-935 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1047058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A memory efficient design is analyzed to derive a low power-area-delay two dimensional (2D) Finite Impulse Response (FIR) filter architecture. The parallel processing concept is introduced in the fully direct-form 2D FIR filter. Due to this, memory reuse is carried out, and it reduces the overall storage memory of the FIR filter. The non-separable 2D FIR filter structure is designed and implemented with block size L and filter length N. The high speed and power efficient multipliers and optimized Carry Look Ahead (CLA) adders are used in the arithmetic module of the FIR filter and a pipelined adder unit is used for the final computation of the filter output. The switch level modification in the logic gates is proposed to reduce the area, power and delay of the adders. This proposed architecture is represented in HDL code and validation is carried out in CADENCE environment using NC Simulator and RTL Compiler synthesis tool. The area, power and delay reports are generated and compared with existing memory efficient 2D FIR filter hardware structures. The power is reduced to 44% and delay is reduced by 20% using Modified CLA (MCLA) adders and pipelining in the design.
Index Terms: 2D-FIR, Low Power Multiplier, Parallel Prefix Adder, CLA, and Memory Reuse.
Scope of the Article: Communication Architectures for Pervasive Computing