Modeling and Design of Cascaded h-bridge type multi-level Inverters up to Thirty-one level for the Reduction and Performance Improvement
K. Ravi Teja1, D.V.N. Ananth2, G. Joga Rao3
1K.Ravi Teja, Department of EEE, Raghu Institute of Technology, Visakhapatnam, India.
2D.V.N. Ananth, Department of EEE, Raghu Institute of Technology, Visakhapatnam, India.
3G. JogaRao, Department of EEE, Raghu Institute of Technology, Visakhapatnam, India.
Manuscript received on May 25, 2020. | Revised Manuscript received on June 29, 2020. | Manuscript published on July 30, 2020. | PP: 26-35 | Volume-9 Issue-2, July 2020. | Retrieval Number: A2739059120/2020©BEIESP | DOI: 10.35940/ijrte.A2739.079220
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Abstract: Multilevel inverter (MLI) becomes more popular in high voltage DC (HVDC) applications, power electronic converters and drives. This paper describes the simulation of single phase multilevel cascaded H-bridge inverter. Simulation of three level, five level, thirteen level, fifteen, twenty-one, thirty-one level inverters are done in MATLAB/ Simulink. The switching schemes, and topologies are discussed in detail here up to thirty-one levels. This paper discusses the voltage level to achieve sinusoidal waveform & compare different voltage level by increasing the level through simulation. The closed loop space-vector based pulse width modulation technique is adopted for effective controlling and lower harmonic voltage conversion. The comparative results are presented for multilevel inverter up-to thirty-one level which shows the total harmonic distortion (THD) is decreased as the number of voltage level rises.
Keywords: Multi-level Inverters, Sinusoidal pulse width modulation, cascaded H-bridge inverter, total harmonic distortion, selective harmonic reduction.