Design and Anlaysis of Low Power Full Adder using 65nm CMOS Technology
K. Paramasivam1, Suresh Kumar N2
1K. Paramasivam, Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
2Suresh Kumar N, Department of Electronics and Communication Engineering, M.A.M School of Engineering, Trichy, (Tamil Nadu), India.
Manuscript received on 11 December 2018 | Revised Manuscript received on 22 December 2018 | Manuscript Published on 09 January 2019 | PP: 124-127 | Volume-7 Issue-4S November 2018 | Retrieval Number: E1884017519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This Paper deals with Low-Power full adder using 65nm CMOS Technology by taking merits of existing full-adders. The proposed one-bit full adder has least power consumption. The proposed adder compared and then analyzed average power, Area and Max power with existing full adder. The designs have been simulated shown results using Tanner EDA tool.
Keywords: CMOS, Area, Average Power.
Scope of the Article: Low-power design