Simulation of Network on Chip for 3D Router Architecture
Navin Kumar Agrawal1, Arpit Jain2, Ambuj Agarwal3
1Navin Kumar Agrawal, Assistant Professor, Department of Computer Science & Engineering, Teerthankar Mahaveer University, Moradabad (Uttar Pradesh), India.
2Dr. Arpit Jain, Assistant Professor, Department of Computer Science & Engineering, Teerthankar Mahaveer University, Moradabad (Uttar Pradesh), India.
3Dr. Ambuj Agarwal, Associate Professor, College of Computing Sciences and Information Technology, Teerthanker Mahaveer University, Moradabad (Uttar Pradesh), India.
Manuscript received on 13 June 2019 | Revised Manuscript received on 09 July 2019 | Manuscript Published on 17 July 2019 | PP: 58-62 | Volume-8 Issue-1C2 May 2019 | Retrieval Number: A10110581C219/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A NoC can be structured and arranged by varioustopologiesin terms of completer organization of the routers and cores and the approaches used to understand the technique for routing, flow control, and switching. The data flow control is related to the data traffic or intensity inside the routers and in the channels. Routing is a techniques or method that defines the optimized path between a data or message to take place from the transmitter to the target end or receiver. The research work focuses on the modeling, simulation and synthesis of mesh and ring topological network. The cluster size of the network is considered as (2 x 2) , (4 x 4), ( 8 x 8), (16 x 16), (32 x 32), (64 x64 ), (128 x 128) and (256 x 256) for 2D NoC design and (2 x 2 x 2) , (4 x 4 x 4), ( 8 x 8 x 8), (16 x 16 x 16), (32 x 32 x 32), (64 x 64×64), (128 x 128 x 128) and (256 x 256 x 256) for 3D NoC router design.
Keywords: Network on Chip (NoC), Router Architecture, System on Chip (SoC).
Scope of the Article: Computer Graphics, Simulation, and Modelling