Design of 13T SRAM Bitcell in 22nm Technology using FinFET for Space Applications
T. R. Dinesh Kumar1, M. Anto Bennet2, R. Aishwarya3, S. Elamathy4, M. Kowsalya5, C. Ranti Bownisha6
1T. R. Dinesh Kumar, Assistant Professor, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
2Dr. M. Anto Bennet, Professor, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
3R. Aishwarya, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
4S. Elamathy, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
5M. Kowsalya, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
6C. Ranti Bownisha, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
Manuscript received on 15 July 2019 | Revised Manuscript received on 11 August 2019 | Manuscript Published on 29 August 2019 | PP: 226-230 | Volume-8 Issue-2S5 July 2019 | Retrieval Number: B10460682S519/2019©BEIESP | DOI: 10.35940/ijrte.B1046.0782S519
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Majority of youngsters’ having connected online through internet either through computers or by smart phones. After the entry of Jio in the field of internet, the competition began and the cost of internet service became much cheaper andnoweveryone SRAM can be found in the cache memory which is a part of the RAM digital to analog converter. SRAM is used for high speed register and some of the small memory banks. The risk of these circuits and memory arrays which are capable to radiation effects than circuits powered at minimal supply voltages. when an high energy particle hits a sensitive node in a circuit soft errors like Single Event Upsets(SEUs)occurs. The attainment of radiation hardening of memory blocks is executing large bit cells or single Error Correcting Codes(ECCs). But ECC may require notable area, performance and leakage power penalties. The favorable device characteristic of FinFET avails them as a popular contender for the replacement of CMOS technologies. An optimal approach to reduce the leakage power of a 13T SRAM cell based on 22nm FinFET technology is proposed in this work . The circuit contains a dual- driven separated feedback mechanism to tolerate the upset with charge of deposits . Better immunity is supplied by this cell to soft errors when compared to 6T SRAM cell.
Keywords: Radiation Hardening, Low Voltage, Critical Charge, Single Event Upset(SEU), FinFET, Static Random Access Memory(SRAM), Memory Array, Soft Errors, Ultra Low Power (ULP).
Scope of the Article: Design and Diagnosis