Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET
K. E. Kaharudin1, Ameer F. Roslan2, F. Salehuddin3, Z. A. F. M. Napiah4, A. S. M. Zain5
1K. E. Kaharudin, MiNE, Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, Durian Tunggal, Melaka.
2Z. A. F. M. Napiah, MiNE, Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, Durian Tunggal, Melaka.
3F. Salehuddin, MiNE, Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, Durian Tunggal, Melaka.
4Ameer F. Roslan, MiNE, Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, Durian Tunggal, Melaka.
5A. S. M. Zain, MiNE, Centre for Telecommunication Research and Innovation (CeTRI), Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, Durian Tunggal, Melaka.
Manuscript received on 21 August 2019 | Revised Manuscript received on 02 September 2019 | Manuscript Published on 16 September 2019 | PP: 783-791 | Volume-8 Issue-2S6 July 2019 | Retrieval Number: B11460782S619/2019©BEIESP | DOI: 10.35940/ijrte.B1146.0782S619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively.
Keywords: Gate Length, on-Current, off-Current, Subthreshold Swing, Transconductance.
Scope of the Article: Low-power design