Error Correction codes Derived from Orthogonal Latin Square Codes
Ande Bhargav1, Y. Varthamanan2
1Ande Bhargav, Reseach Scholar, Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai (Tamil Nadu), India.
2Dr. Y. Varthamanan, Associate Professor, Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai (Tamil Nadu), India.
Manuscript received on 25 August 2019 | Revised Manuscript received on 11 September 2019 | Manuscript Published on 17 September 2019 | PP: 1948-1952 | Volume-8 Issue-2S8 August 2019 | Retrieval Number: B12050882S819/2019©BEIESP | DOI: 10.35940/ijrte.B1205.0882S819
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The developments in IC technology and rapid increase of transistor densities and scaling factor, the use of ECC’s acquired prominence. Multiple bit errors in memories due to technology scaling demands advanced error correction codes. SEC-DEC, DEC, burst error detection, Golay code, Reed Solmon codes etc. have much decoding complexity and latency. The above drawbacks can be reduced with OLS codes. OLS codes with majority logic decoding technique, modular construction and simple decoding mechanisms it enables low delay improvements. MBU’S can be addressed using OLS-MLD codes. This paper presents a detail study of developments in multibit ECC’s using OLS-MLD mechanism.
Keywords: Component; Error Correction Codes; Single Error Correction – Double Error Detection; Orthogonal Latin Squares; Majority Logic Decodable.
Scope of the Article: Component-Based Software Engineering