Performance Research on Variable Data Rate Reconfigurable Architecture for SDR Receiver
Nataraj URS1, R Venkatasiva Reddy2
1Nataraj URS H D, Associate Professor, & Research Scholor, School of ECE, REVA University, Bangalore (Karnataka), India.
2Dr. R Venkatasiva Reddy, Professor, School of ECE, REVA University Bangalore (Karnataka), India.
Manuscript received on 19 August 2019 | Revised Manuscript received on 10 September 2019 | Manuscript Published on 17 September 2019 | PP: 1008-1011 | Volume-8 Issue-2S8 August 2019 | Retrieval Number: B10020882S819/2019©BEIESP | DOI: 10.35940/ijrte.B1002.0882S819
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In Early days, communications systems used amplitude and frequency modulation schemes in which bandwidth constraint is one of the major challenge to accommodate more data rates. As the data rate requirement increased drastically till date, The applications demands more data rates for communication using less bandwidth is considered as an efficient communication system. For achieving communication with high data rates using less bandwidth, technology migrated to digital modulation schemes. In this phase new modulation techniques like ASK, FSK, PSK were realised. ASK and FSK modulation schemes bandwidth efficiency is less as compared to PSK schemes. For best utilisation of bandwidth efficiency and less inherent noise levels, PSK schemes are used, which is suitable for high data rate applications. In this paper QPSK modulation and demodulation technique is selected for realising the variable data rate in the range of 1.2MBPS as the best bandwidth with efficient reconfigurable architecture designed for software defined radio receiver.
Keywords: Modulation, SDR, QPSK, QAM, FPGA, Reconfigurable Architecture.
Scope of the Article: Data Mining and Warehousing