Low Power MAC Unit for DSP Processor
Avisek Sen1, Partha Mitra2, Debarshi Datta3
1Avisek Sen, Asst. Prof., Department of Electronics & Communication, Brainware Group of Institutions, WBUT, Kolkata (West Bengal), India.
2Partha Mitra, Asst. Prof., Department of Electronics & Communication, Brainware Group of Institutions, WBUT, Kolkata (West Bengal), India.
3Debarshi Datta, Asst. Prof., Department of Electronics & Communication, Brainware Group of Institutions, WBUT, Kolkata (West Bengal), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 93-95 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0434021613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power dissipation is one of the most important design objectives in integrated circuit, after speed. Digital signal processing (DSP) circuits whose main building block is a Multiplier-Accumulator (MAC) unit. High speed and low power MAC unit is desirable for any DSP processor. This is because speed and throughput rate are always the concerns of DSP system. This paper explores the design of low power MAC unit with block enable technique to reduce power dissipation. The MAC unit is implemented using 130-nm CMOS process technology. The whole MAC chip is operated at 200 MHz with1.5V supply voltage. The result analysis shows that the power consumption is reduced by using block enable technique.
Keywords: Adders, Block Enable, CAD Tools, Low Power, MAC, Multipliers.
Scope of the Article: Low-power Design