AXI Acquiescent DDR3 SDRAM Memory Controller
N. V. Apparao1, V. Narasimharao2
1N. V. Apparao, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, (Andhra Pradesh), India.
2V. Narasimharao, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, (Andhra Pradesh), India.
Manuscript received on 20 September 2014 | Revised Manuscript received on 30 September 2014 | Manuscript published on 30 September 2014 | PP: 6-9 | Volume-3 Issue-4, September 2014 | Retrieval Number: D1193093414/2014©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper describes the implementation of AXI acquiescent DDR3 memory controller. It discusses the overall architecture of the DDR3 controller; it also discusses the AXI protocol operation. The DDR3 memory controller compares with DDR1 and DDR2 in performance wise. The design is simulated and synthesized on Xilinx ISE 13.2 successfully.
Keyword: AXI Interface, DDR3 memory, AXI protocol operation, AXI access Manager
Scope of the Article: Routing and Transport Protocols