Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and Kogge Stone Adder
Surbhi Nema1, Pramod Kumar Jain2, Devendra Singh Ajnar3
1Surbhi Nema1, PG Student1, Dept of Electronics & Instrumentation, Shri Govindram Seksaria Institute of Technology & Science, Indore, (M.P.), India.
2Pramod Kumar Jain, Associate Professor, Dept of Electronics & Instrumentation, Shri Govindram Seksaria Institute of Technology & Science, Indore, (M.P.), India.
3Devendra Singh Ajnar, Associate Professor, Dept of Electronics & Instrumentation, Shri Govindram Seksaria Institute of Technology & Science, Indore, (M.P.), India
Manuscript received on 13 March 2019 | Revised Manuscript received on 18 March 2019 | Manuscript published on 30 July 2019 | PP: 6138-6141 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3731078219/19©BEIESP | DOI: 10.35940/ijrte.B3731.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: 32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.
Keywords: FIR Filter, Vedic Multiplier, Kogge Stone Adder, Delay & VHDL.
Scope of the Article: VLSI Algorithms