Functional Verification and the Physical Design of MIPS Architecture
B. Kiran Kumar1, Anilkumar B2
1B. Kiran Kumar, ECE, GMR Institute of Technology, GMR Nagar, Rajam, AP, India.
1B. Anil Kumar, ECE, GMR Institute of Technology, GMR Nagar Rajam, AP, India.
Manuscript 2eceived on 03 March 2019 | Revised Manuscript received on 09 March 2019 | Manuscript published on 30 July 2019 | PP: 3151-3154 | Volume-8 Issue-2, July 2019 | Retrieval Number: B2867078219/19©BEIESP | DOI: 10.35940/ijrte.B2867.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Microprocessor with no Interlocked Pipeline Stages (MIPS) is Reduced Instruction Set Computation (RISC) based architecture. The RISC is composed of a smallest set of instructions for increasing the speed processor. In this work, functional verification and physical design of the 32-bit 5-stage pipelined MIPS processor is proposed to be done. Here, the physical design is aimed to improve the area, power and speed performance of the design. Cadence SOC encounter is proposed to use for the physical design of the MIPS architecture. Also, this work explores the complete the ASIC flow from RTL to GDSII for MIPS processor using TSMC (Taiwan semiconductor Manufacture Company) 90nm technology. Finally, performance of the proposed implementation will be compared with the existing implementations.
Index Terms: Interlocked Pipeline Stages, ASIC Flow, MIPS, RISC.
Scope of the Article: Discrete Optimization