Implementing Static and Dynamic Full Adders in Dynamic Body Biasing Technology
Preeti Singh1, Shobha Sharma2
1Preeti Singh, Electronics and Communication, Indira Gandhi Delhi Technical University for women, Delhi, India.
2(Dr Shobha Sharma, Corresponding Author), Faculty, Electronics and Communication, Indira Gandhi Delhi Technical University for women, Delhi, India.
Manuscript received on 07 March 2019 | Revised Manuscript received on 14 March 2019 | Manuscript published on 30 July 2019 | PP: 498-502 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1562078219/19©BEIESP | DOI: 10.35940/ijrte.B1562.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we proposed the new technology for good performance and high speed. We used dynamic body biasing implemented static and dynamic full adders. This is very useful for threshold voltage decrease by the dynamic body biasing which has good benefit for decrease delay of the circuits. The proposed method provides less power and delay. In Full Adder implementation CMOS technology at 180 nm is used. Simulation is done by cadence virtuoso tool. New static and dynamic Full Adders have been suggested in this paper. We have implemented 8 bit static and dynamic full adder in 180 nm Dynamic Threshold CMOS technology. The proposed DTMOS circuits are faster than existing Full Adder circuits.
Index Terms: DTMOS, Domino Logic, Full Adder, Delay, Static, Dynamic, Power Delay Product [PDP], and Power
Scope of the Article: Foundations Dynamics