Design and Performance Evaluation of Ideal and Non-Ideal Effects of Pipeline ADC using Software Reference Models
Kiran B1, Vaibhav A Meshram2
1Kiran B, Department of Electronics Engineering, JAIN (Deeme-to-be University), Bengaluru, India.
2Vaibhav A Meshram, Department of Electronics and Communication Engineering, Dayanand Sagar University, Bengaluru, India.
Manuscript received on 05 August 2019. | Revised Manuscript received on 10 August 2019. | Manuscript published on 30 September 2019. | PP: 8386-8391 | Volume-8 Issue-3 September 2019 | Retrieval Number: C6517098319/2019©BEIESP | DOI: 10.35940/ijrte.C6517.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Analog-to-digital converter (ADC) is one of the key component in any of the application oriented system design. This paper mainly focused on the simulation of various non-ideal parameters of an ADC as the number of resolution increases. The effect of non-ideal aspects like Jitter model and error block model are created in Matlab Simulink and the results are plotted. The dynamic non-ideal characteristics are discussed with their mathematical models and are compared with the equivalent resolution ADCs. The preliminary observations are also drawn according to the ideal characteristics. This shows that as the resolution increases, the bandwidth of non-ideal characteristics are also increases. This work is entitled to prove the non-idealities of 12-bit Pipeline ADC.
Keywords: Pipeline ADC, Dynamic Error, Harmonic Distortion, SFDR, Gain error, Offset Error, DNL and INL, Sample and Hold, Thermal noise.
Scope of the Article: High Performance Computing