On-Chip Hardware Accelerator For DSP Applications
Swati Sanjay Patil1, Nagaraja B. G2
1Swati Sanjay Patil , Jayawantrao Sawant Polytechnic, Hadapsar, Pune, Maharashtra, India.
2Nagaraja B. G, Jain Institute of Technology, Davanagere, Karnataka, India.
Manuscript received on 01 August 2019. | Revised Manuscript received on 05 August 2019. | Manuscript published on 30 September 2019. | PP: 7534-7538 | Volume-8 Issue-3 September 2019 | Retrieval Number: C6079098319/19©BEIESP | DOI: 10.35940/ijrte.C6079.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: High speed computing systems developed for multimedia streaming application demand high throughput and which can be achieved by designing hardware accelerators for data processing. This article presents new hardware accelerating platform comprised of heterogeneous multi core processing elements integrated on single chip FPGA. This kind of multi core platform can boost multimedia applications through parallel processing. The proposed multi core platform has been realized on FPGA and few DSP applications are executed on the processing elements of the platform to validate its performance. The performance of the proposed hardware accelerator has been compared with existing standard computing platforms frequently used for multimedia applications. The comparison shows that the proposed on-chip multi core accelerator has enhanced the execution speed of DSP applications while providing optimum throughput.
Keywords: Hardware Accelerator, Multimedia Computing Systems, FPGA, Custom Computing Cores, Reconfigurable Architectures, General Purpose Processors.
Scope of the Article: High Performance Computing