High Speed FIR Filter Design using Multiplier Sharing and Sub Expression Elimination Method
Chitra M1, Priyanka S2, Prabha V C3, Ramya S4
1Chitra M, Assistant Professor, Department of ECE, Kongu Engineering College, Perundurai, Erode, Tamil Nadu, India.
2Priyanka S, Student, Department of ECE, Kongu Engineering College, Perundurai, Erode. Tamil Nadu, India.
3K.N.Vardhan, Student, Department of ECE, Kongu Engineering College, Perundurai, Erode, Tamil Nadu, India.
4Ramya S Student, Department of ECE, Kongu Engineering College, Perundurai, Erode, Tamil Nadu, India.
Manuscript received on November 20, 2019. | Revised Manuscript received on November 28, 2019. | Manuscript published on 30 November, 2019. | PP: 7414-7417 | Volume-8 Issue-4, November 2019. | Retrieval Number: D5310118419/2019©BEIESP | DOI: 10.35940/ijrte.D5310.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: FIR filter is the basic filter used in many DSP applications because of its linear phase , stability , low cost and simple structure . Designing a high- speed and hardware efficient FIR filter is a very difficult task as the complexity increases with the filter order .In most Application the higher order filters are required but the memory usage of filter increases exponentially with the order of the filter using multipliers occupy a large chip area and need more access time. So the design and implementation of highly efficient look up table (LUT) based circuit for the implementation using DA Algorithm increases the speed. Multiplier sharing and sub-expression elimination methods are proposed to optimize the Structural adders. These methods split the structural adders into smaller adder blocks to reduce the delay. In order to reduce the complexity of structural adders round-off can be performed at the cost of sacrificing precision of the filter.
Keywords: FIR filter, Look Up Table(LUT),Multiplier Sharing Method(MSM) , Sub-expression Elimination Method(SEM).
Scope of the Article: FPGAs.